1. Field of the Invention
The present invention relates to a serial-to-parallel conversion (SPC) circuit for converting the serial digital data into the parallel digital data. It also relates to a semiconductor device including the SPC circuit.
2. Description of the Related Art
An example of a semiconductor device whose input signals are digital data, is a liquid crystal display device of active matrix type. In recent years, the active matrix type liquid crystal display device has come to be constructed of a plurality of TFTs (thin film transistors) formed from polycrystalline silicon, and to be unitarily formed with an active matrix circuit for displaying an image and driver circuits for driving the active matrix circuit.
A serial-to-parallel conversion (SPC) circuit for digital data receives the inputs of digital data (hereinbelow, termed “input digital data”) as the input signals, and feeds the source signal line driver circuit of the active matrix type liquid crystal display device with digital data modified by temporally expanding the pulse length of the input digital data (the pulse length may be expanded any times, but it is most commonly expanded n times where letter n denotes a natural number of at least 2). The temporal expansion of the pulse length of the input digital data to n times is nothing but lowering the frequency of the input digital data to 1/n.
The SPC circuit for digital data has significance as stated below. The digital data to be inputted to the active matrix type liquid crystal display device are ordinarily at several tens MHz, but the digital data at one hundred and several tens MHz might be generalized in compliance with recent requirements for a higher definition, a higher resolution and more gradations.
Nevertheless, the TFTs included in the source signal line driver circuit of the active matrix type liquid crystal display device have had performances insufficient for processing the digital data of such a higher frequency, and they have been incapable of operating or have had difficulty in reliability. It is accordingly indispensable to lower the frequency of the input digital signals down to the degree at which the source signal line driver circuit is capable of operating to perfection. In this regard, the SPC circuit for digital data functions to lower the frequency of the input digital data. Incidentally, the scale of the SPC circuit for digital data is smaller as compared with that of the source signal line driver circuit, and a clock signal within the SPC circuit is less liable to become “dull” (as a signal delay at the rise or fall of the pulse of the clock signal), so that the SPC circuit can be driven at a higher speed.
As stated above, the SPC circuit for digital data can be driven faster than the source signal line driver circuit etc. The faster operation of the SPC circuit, however, has been somewhat objectionable in the points of reliability and stability in complying with the recent requirements for a higher definition, a higher resolution and more gradations.
An example of the SPC circuit for digital data having hitherto been used by the inventors is an SPC circuit for digital data disclosed in Japanese Patent Application Laid-open No. 11-231798 (1999), assigned to the same assignee as that of the present application. The Japanese Patent Application corresponds to a U.S. patent application Ser. No. 09/206,297 and a European Patent Application Laid-open No. 0 921 517 A.
The exemplified SPC circuit for digital data necessitates for its operation a clock signal at the same frequency as that of the input digital data. By way of example, in order to convert the serially inputted digital data of 80 MHz into eight parallel digital data, the SPC circuit is normally fed with the clock signal of 80 MHz. The operation has been problematic in power dissipation, stability, reliability, etc.